1. Field of the Invention
This application relates to integrated circuit devices more particularly to integrated circuits utilized in generating clock signals and systems incorporating such circuits.
2. Description of the Related Art
Clock sources typically utilize a resonator such as a crystal oscillator or surface acoustic wave (SAW) device. Precision in traditional clock sources utilizing crystal oscillators is determined by the accuracy of the cut of the crystal and the calibration performed after the cut. For example, frequency tuning may be achieved by sputtering gold onto the crystal after cutting the crystal. Fixed frequency sources such as crystals have typically provided better phase noise performance than the phase noise performance associated with variable frequency source such as, e.g., a voltage controlled oscillator (VCO). That is due, at least in part, to the fact that the variable elements (e.g., the varactor) associated with the VCO used to vary the frequency typically have higher losses than fixed elements such as the capacitors in a fixed source.
However, resonators typically have a limited optimum range due to manufacturing constraints, i.e., in general, it is difficult to pull an oscillating frequency of a crystal to a target frequency from a wide range of frequencies. However, various applications have requirements for numerous frequencies outside of the pull range of a resonator. Typically, a different frequency range will require a different resonator. Accuracy requirements vary for clock sources, but are typically in the parts per million (ppm) range.
The drive to design network equipment with multi-service capable interfaces has dramatically increased the complexity of the timing subsystems. In addition to standard Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) rates, these new systems must now support a diverse set of line rates including 10 Gbps Ethernet, 10 Gbps Fibre Channel, as well as the associated forward error correction (FEC) rates. Requirements to support these new data rates is forcing timing subsystem designers to develop timing sources capable of providing an expanded set of low jitter, high frequency (frequencies of 622 MHz or greater) reference clocks for use across the data processing chain from physical layer to backplane transceiver. A summary of common line rates and the associated board level reference clock frequencies is provided in Table 1. Since these frequencies are not related by a simple integer ratio, designers must rely on multiple discrete oscillators or sophisticated phase-locked loops (PLLs) to support the various reference clock generation requirements in multi-protocol systems. Note that many of the line rates are around 10 Gbits per second.
TABLE 1ForwardRequiredDataErrorLineOscillatorRateCorrectionRateFrequenciesProtocol(Gbps)(FEC) Ratio(Gbps)(MHz)SONET OC-192, SDH9.95—9.95622.08, 155.52STM-64G.975 (4 × OC-48 +9.95255/23810.66666.51, 166.63FEC)OTN OTU2 (G.709)9.95255/23710.71669.33, 167.3310 Gbps Ethernet LAN10.31—10.31644.53, 161.1310.31255/23811.04690.57, 172.6410.31255/23711.10693.48, 173.3710 Gbps Fibre Channel10.52—10.52657.42, 164.3510.52255/23711.32707.35, 176.83
Using conventional oscillator technology, the system timing architectures of multi-service systems become unwieldy as the number of oscillators grows to support an expanded set of line rates.
Clock scaling PLLs are critical timing subsystems because they perform the clock scaling required to synchronize the data transmission rates between the client side and the line side. The design of these PLLs is difficult because they must provide non-integer clock scaling, operate at high frequencies (>600 MHz), provide low jitter (<0.3 ps RMS), and cover a range of frequencies that span approximately 100 MHz. To meet the jitter requirements, discrete voltage controlled SAW oscillators (VCSOs) or high frequency fundamental (HFF) voltage controlled oscillators (VCXOs) must be used in the PLL circuit. Since these devices are only capable of operating within a few hundred parts per million (ppm) of a center frequency, multi-protocol support requires a bank of VCSOs or VCXOs to support the range of input to output frequency translations required. In addition, special care must be taken during the design and layout of the PLL circuit to accommodate variations in VCSO electrical performance like voltage gain (Kv) and prevent noise coupling between VCSOs and other board level components.
These crystal and SAW based oscillators introduce various reliability issues including temperature drift and long term aging. If the temperature drift or aging causes the frequency to drift beyond the pull range of the oscillator, the timing subsystem may need replacement. Thus, it would be desirable to be able to expand the pull range of these oscillators to account for aging and temperature effects in timing subsystems.